# vsim -L lib -L vunit_lib -modelsimini d:/Programming/github/vunit/vunit/vhdl/check/vunit_out/modelsim/modelsim.ini -onfinish stop -quiet -t ps -wlf d:/Programming/github/vunit/vunit/vhdl/check/vunit_out/tests/lib.tb_check_sequence/modelsim/vsim.wlf {-g/tb_check_sequence/runner_cfg="enabled_test_cases : Test should fail on sequences shorter than two events,,Test should pass a most triggered pipelined and sequentially asserted event sequence,,Test should fail a most triggered but interrupted event sequence,,Test should pass a first triggered pipelined and sequentially asserted event sequence when pipelining is supported,,Test should fail a first triggered but interrupted event sequence,,Test should ignore a first triggered and simulataneously initiated event sequence when pipelining is not supported,,Test should fail on unknowns in event sequence,,Test should support weak high and low meta values,,Test should handle reversed and or offset expressions,output path : d::/Programming/github/vunit/vunit/vhdl/check/vunit_out/tests/lib.tb_check_sequence/,active python runner : true"} lib.tb_check_sequence(test_fixture) 
# ** Note: 
# -----------
# Test result
# -----------
#    Time: 641 ns  Iteration: 0  Instance: /tb_check_sequence
# ** Note: Number of assertions: 54
#    Time: 641 ns  Iteration: 0  Instance: /tb_check_sequence
# ** Note: Number of errors: 0
#    Time: 641 ns  Iteration: 0  Instance: /tb_check_sequence
# Break in Subprogram vunit_stop at D:/Programming/github/vunit/vunit/vhdl/run/src/stop_body_2008.vhd line 10
# Stopped at D:/Programming/github/vunit/vunit/vhdl/run/src/stop_body_2008.vhd line 10 
