# vsim -L lib -L vunit_lib -modelsimini d:/Programming/github/vunit/vunit/vhdl/check/vunit_out/modelsim/modelsim.ini -onfinish stop -quiet -t ps -wlf d:/Programming/github/vunit/vunit/vhdl/check/vunit_out/tests/lib.tb_check_match/modelsim/vsim.wlf {-g/tb_check_match/runner_cfg="enabled_test_cases : Test should pass on unsigned matching unsigned,,Test should fail on unsigned not matching unsigned,,Test should pass on std_logic_vector matching std_logic_vector,,Test should fail on std_logic_vector not matching std_logic_vector,,Test should pass on signed matching signed,,Test should fail on signed not matching signed,,Test should pass on std_logic matching std_logic,,Test should fail on std_logic not matching std_logic,output path : d::/Programming/github/vunit/vunit/vhdl/check/vunit_out/tests/lib.tb_check_match/,active python runner : true"} lib.tb_check_match(test_fixture) 
# Break in Subprogram vunit_stop at D:/Programming/github/vunit/vunit/vhdl/run/src/stop_body_2008.vhd line 10
# Stopped at D:/Programming/github/vunit/vunit/vhdl/run/src/stop_body_2008.vhd line 10 
