# vsim -L lib -L vunit_lib -modelsimini d:/Programming/github/vunit/vunit/vhdl/check/vunit_out/modelsim/modelsim.ini -onfinish stop -quiet -t ps -wlf d:/Programming/github/vunit/vunit/vhdl/check/vunit_out/tests/lib.tb_check_false/modelsim/vsim.wlf {-g/tb_check_false/runner_cfg="enabled_test_cases : Test should fail on true and logic 1 inputs to sequential checks,,Test should pass on false and logic 0 inputs to sequential checks,,Test should be possible to use concurrently,,Test should be possible to use concurrently with negative active clock edge,,Test should be possible to use concurrently with custom checker,,Test should pass on weak low but fail on other meta values,,Test should pass on logic high inputs when not enabled,output path : d::/Programming/github/vunit/vunit/vhdl/check/vunit_out/tests/lib.tb_check_false/,active python runner : true"} lib.tb_check_false(test_fixture) 
# ** Note: 
# -----------
# Test result
# -----------
#    Time: 261 ns  Iteration: 0  Instance: /tb_check_false
# ** Note: Number of assertions: 80
#    Time: 261 ns  Iteration: 0  Instance: /tb_check_false
# ** Note: Number of errors: 0
#    Time: 261 ns  Iteration: 0  Instance: /tb_check_false
# Break in Subprogram vunit_stop at D:/Programming/github/vunit/vunit/vhdl/run/src/stop_body_2008.vhd line 10
# Stopped at D:/Programming/github/vunit/vunit/vhdl/run/src/stop_body_2008.vhd line 10 
